The present invention relates to field programmable matrix circuits which have a plurality of noninverted and inverted input lines which can be programmably coupled to a plurality of column lines.
Programmable matrix circuits are well known in the art. A typical programmable matrix circuit has a plurality of row lines, each of which can be coupled to one or more of a plurality of column lines. Typically, programmable matrix circuits are used in a logic array or in a memory. In a logic array, the inputs are provided in pairs, with a noninverted and an inverted input for each pair. Memory circuits do not have this pairing characteristic.
In a typical logic array, a single column is used as the output of a logic gate, such as a NOR gate, and is referred to as a term line. The inputs which are coupled to that column provide the inputs to the logic gate. The particular inputs which are coupled to a column (term) can be programmed by selecting the desired inputs to be coupled to that column. An example of the use of a programmable matrix circuit in a programmable logic array is shown in U.S. Pat. No. 4,124,899.
In the prior art, the programmability of the matrix circuit is accomplished by using a transistor to provide a coupling link between each and every row line and each and every column line. If it is desired to affect the state of a column with a particular row, then the transistor at the row-column intersection is enabled. Conversely, if a particular row is not to affect the state of a column, the transistor is disabled. The enablement or disablement of the transistor can be accomplished in a number of ways, and can be accomplished in the factory or in the field by the customer. In the factory, to disable a transistor, it could, for instance, be left out entirely during the fabrication process or any one of certain structures which comprise the transistor can be omitted during the fabrication process. In this way, an operational transistor is not created and the transistor's operation is in effect disabled. The transistor can also be enabled by providing a metal connection to the column during the metal masking step. U.S. Pat. No. 4,495,590 to Mitchell, Jr. shows a matrix in which a transistor has its gate terminal selectively coupled to one of true and complement lines or unconnected, presumably at the metal mask stage of production.
Alternatively, the transistor can be enabled or disabled in the field by a customer. For instance, an operational transistor can be connected to the column via a fusible link which may be made nonconductive by blowing the fuse. Alternately, all the transistors can be operationally connected and can be selectively enabled or disabled by a charged storage mechanism such as those used in EPROM (Electrically Programmable Read Only Memory) or EEPROM (Electrically Erasable Programmable Read Only Memory) technology.
For the field programmable devices, there is always a single transistor per input line for each column line. The disadvantage of this prior art technique is that for many logic applications there results an excessive logic propagation delay. The propagation delay is dependent upon the rate at which the column changes voltage levels following an input transition. The change in voltage per unit time, or slew rate, of the column following activation or deactivation of a transistor is proportional to the ratio of the conductance of the transistor to the total column capacitance. The column capacitance is in turn dependent upon the capacitance of each transistor coupled to the column and thus the number of pull-down transistors on the column. In the field, unlike in the factory, it is not possible to simply leave out the unused transistors or leave out their metal connections.